Struct rp2040_pac2::pwm::Pwm

pub struct Pwm(pub *mut u8);

Simple PWM

Implementations

impl Pwm

pub fn ch0_csr(self) -> Reg<Ch0Csr, RW>

Control and status register

pub fn ch0_div(self) -> Reg<Ch0Div, RW>

INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.

pub fn ch0_ctr(self) -> Reg<Ch0Ctr, RW>

Direct access to the PWM counter

pub fn ch0_cc(self) -> Reg<Ch0Cc, RW>

Counter compare values

pub fn ch0_top(self) -> Reg<Ch0Top, RW>

Counter wrap value

pub fn ch1_csr(self) -> Reg<Ch1Csr, RW>

Control and status register

pub fn ch1_div(self) -> Reg<Ch1Div, RW>

INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.

pub fn ch1_ctr(self) -> Reg<Ch1Ctr, RW>

Direct access to the PWM counter

pub fn ch1_cc(self) -> Reg<Ch1Cc, RW>

Counter compare values

pub fn ch1_top(self) -> Reg<Ch1Top, RW>

Counter wrap value

pub fn ch2_csr(self) -> Reg<Ch2Csr, RW>

Control and status register

pub fn ch2_div(self) -> Reg<Ch2Div, RW>

INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.

pub fn ch2_ctr(self) -> Reg<Ch2Ctr, RW>

Direct access to the PWM counter

pub fn ch2_cc(self) -> Reg<Ch2Cc, RW>

Counter compare values

pub fn ch2_top(self) -> Reg<Ch2Top, RW>

Counter wrap value

pub fn ch3_csr(self) -> Reg<Ch3Csr, RW>

Control and status register

pub fn ch3_div(self) -> Reg<Ch3Div, RW>

INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.

pub fn ch3_ctr(self) -> Reg<Ch3Ctr, RW>

Direct access to the PWM counter

pub fn ch3_cc(self) -> Reg<Ch3Cc, RW>

Counter compare values

pub fn ch3_top(self) -> Reg<Ch3Top, RW>

Counter wrap value

pub fn ch4_csr(self) -> Reg<Ch4Csr, RW>

Control and status register

pub fn ch4_div(self) -> Reg<Ch4Div, RW>

INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.

pub fn ch4_ctr(self) -> Reg<Ch4Ctr, RW>

Direct access to the PWM counter

pub fn ch4_cc(self) -> Reg<Ch4Cc, RW>

Counter compare values

pub fn ch4_top(self) -> Reg<Ch4Top, RW>

Counter wrap value

pub fn ch5_csr(self) -> Reg<Ch5Csr, RW>

Control and status register

pub fn ch5_div(self) -> Reg<Ch5Div, RW>

INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.

pub fn ch5_ctr(self) -> Reg<Ch5Ctr, RW>

Direct access to the PWM counter

pub fn ch5_cc(self) -> Reg<Ch5Cc, RW>

Counter compare values

pub fn ch5_top(self) -> Reg<Ch5Top, RW>

Counter wrap value

pub fn ch6_csr(self) -> Reg<Ch6Csr, RW>

Control and status register

pub fn ch6_div(self) -> Reg<Ch6Div, RW>

INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.

pub fn ch6_ctr(self) -> Reg<Ch6Ctr, RW>

Direct access to the PWM counter

pub fn ch6_cc(self) -> Reg<Ch6Cc, RW>

Counter compare values

pub fn ch6_top(self) -> Reg<Ch6Top, RW>

Counter wrap value

pub fn ch7_csr(self) -> Reg<Ch7Csr, RW>

Control and status register

pub fn ch7_div(self) -> Reg<Ch7Div, RW>

INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.

pub fn ch7_ctr(self) -> Reg<Ch7Ctr, RW>

Direct access to the PWM counter

pub fn ch7_cc(self) -> Reg<Ch7Cc, RW>

Counter compare values

pub fn ch7_top(self) -> Reg<Ch7Top, RW>

Counter wrap value

pub fn en(self) -> Reg<En, RW>

This register aliases the CSR_EN bits for all channels. Writing to this register allows multiple channels to be enabled or disabled simultaneously, so they can run in perfect sync. For each channel, there is only one physical EN register bit, which can be accessed through here or CHx_CSR.

pub fn intr(self) -> Reg<Intr, RW>

Raw Interrupts

pub fn inte(self) -> Reg<Inte, RW>

Interrupt Enable

pub fn intf(self) -> Reg<Intf, RW>

Interrupt Force

pub fn ints(self) -> Reg<Ints, RW>

Interrupt status after masking & forcing

Trait Implementations

impl Clone for Pwm

fn clone(&self) -> Pwm

Returns a copy of the value.

pub fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for Pwm

impl Send for Pwm

impl Sync for Pwm