Crate rp2040_pac2[−][src]
Peripheral access API (generated using svd2rust v0.17.0 (426f4c8 2021-03-17))
Modules
| adc | |
| busctrl | |
| clocks | |
| dma | |
| generic | |
| i2c | |
| io | |
| pads | |
| pio | |
| pll | |
| psm | |
| pwm | |
| resets | |
| rosc | |
| rtc | |
| sio | |
| spi | |
| syscfg | |
| sysinfo | |
| tbman | |
| timer | |
| uart | |
| usb | |
| vreg_and_chip_reset | |
| watchdog | |
| xip_ctrl | |
| xip_ssi | |
| xosc |
Enums
| Interrupt |
Constants
| ADC | Control and data interface to SAR ADC |
| BUSCTRL | Register block for busfabric control signals and performance counters |
| CLOCKS | |
| DMA | DMA with separate read and write masters |
| I2C0 | DW_apb_i2c address block |
| I2C1 | |
| IO_BANK0 | |
| IO_QSPI | |
| NVIC_PRIO_BITS | Number available in the NVIC for configuring priority |
| PADS_BANK0 | |
| PADS_QSPI | |
| PIO0 | Programmable IO block |
| PIO1 | |
| PLL_SYS | |
| PLL_USB | |
| PSM | |
| PWM | Simple PWM |
| RESETS | |
| ROSC | |
| RTC | Register block to control RTC |
| SIO | Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access. |
| SPI0 | |
| SPI1 | |
| SYSCFG | Register block for various chip control signals |
| SYSINFO | |
| TBMAN | Testbench manager. Allows the programmer to know what platform their software is running on. |
| TIMER | Controls time and alarms time is a 64 bit value indicating the time in usec since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq |
| UART0 | |
| UART1 | |
| USBCTRL_REGS | USB FS/LS controller device registers |
| VREG_AND_CHIP_RESET | control and status for on-chip voltage regulator and chip level reset subsystem |
| WATCHDOG | |
| XIP_CTRL | QSPI flash execute-in-place block |
| XIP_SSI | DW_apb_ssi has the following features: * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation. * APB3 and APB4 protocol support. * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits. * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices. * Programmable Dual/Quad/Octal SPI support in Master Mode. * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation. * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes. * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes. * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests. * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently. * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus. * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains. * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates. * Programmable features: - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire. - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation. - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer. * Configured features: - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits. - 1 slave select output. - Hardware slave-select – Dedicated hardware slave-select line. - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller. - Interrupt polarity – active high interrupt lines. - Serial clock polarity – low serial-clock polarity directly after reset. - Serial clock phase – capture on first edge of serial-clock directly after reset. |
| XOSC | Controls the crystal oscillator |