Struct rp2040_pac2::pll::regs::Cs

#[repr(transparent)]pub struct Cs(pub u32);

Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=400MHz, max=1600MHz

Implementations

impl Cs

pub const fn lock(&self) -> bool

PLL is locked

pub fn set_lock(&mut self, val: bool)

PLL is locked

pub const fn bypass(&self) -> bool

Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.

pub fn set_bypass(&mut self, val: bool)

Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.

pub const fn refdiv(&self) -> u8

Divides the PLL input reference clock. Behaviour is undefined for div=0. PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.

pub fn set_refdiv(&mut self, val: u8)

Divides the PLL input reference clock. Behaviour is undefined for div=0. PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.

Trait Implementations

impl Clone for Cs

fn clone(&self) -> Cs

Returns a copy of the value.

pub fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for Cs

impl Default for Cs

fn default() -> Cs

Returns the “default value” for a type.