Module rp2040_pac2::pll::regs

Structs

Cs	Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=400MHz, max=1600MHz
FbdivInt	Feedback divisor (note: this PLL does not support fractional division)
Prim	Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) the primary output is driven from VCO divided by postdiv1*postdiv2
Pwr	Controls the PLL power modes.