Struct rp2040_pac2::xip_ssi::XipSsi

pub struct XipSsi(pub *mut u8);

DW_apb_ssi has the following features: * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation. * APB3 and APB4 protocol support. * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits. * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices. * Programmable Dual/Quad/Octal SPI support in Master Mode. * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation. * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes. * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes. * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests. * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently. * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus. * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains. * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates. * Programmable features: - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire. - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation. - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer. * Configured features: - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits. - 1 slave select output. - Hardware slave-select – Dedicated hardware slave-select line. - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller. - Interrupt polarity – active high interrupt lines. - Serial clock polarity – low serial-clock polarity directly after reset. - Serial clock phase – capture on first edge of serial-clock directly after reset.

Implementations

impl XipSsi

pub fn ctrlr0(self) -> Reg<Ctrlr0, RW>

Control register 0

pub fn ctrlr1(self) -> Reg<Ctrlr1, RW>

Master Control register 1

pub fn ssienr(self) -> Reg<Ssienr, RW>

SSI Enable

pub fn mwcr(self) -> Reg<Mwcr, RW>

Microwire Control

pub fn ser(self) -> Reg<Ser, RW>

Slave enable

pub fn baudr(self) -> Reg<Baudr, RW>

Baud rate

pub fn txftlr(self) -> Reg<Txftlr, RW>

TX FIFO threshold level

pub fn rxftlr(self) -> Reg<Rxftlr, RW>

RX FIFO threshold level

pub fn txflr(self) -> Reg<Txflr, RW>

TX FIFO level

pub fn rxflr(self) -> Reg<Rxflr, RW>

RX FIFO level

pub fn sr(self) -> Reg<Sr, RW>

Status register

pub fn imr(self) -> Reg<Imr, RW>

Interrupt mask

pub fn isr(self) -> Reg<Isr, RW>

Interrupt status

pub fn risr(self) -> Reg<Risr, RW>

Raw interrupt status

pub fn txoicr(self) -> Reg<Txoicr, RW>

TX FIFO overflow interrupt clear

pub fn rxoicr(self) -> Reg<Rxoicr, RW>

RX FIFO overflow interrupt clear

pub fn rxuicr(self) -> Reg<Rxuicr, RW>

RX FIFO underflow interrupt clear

pub fn msticr(self) -> Reg<Msticr, RW>

Multi-master interrupt clear

pub fn icr(self) -> Reg<Icr, RW>

Interrupt clear

pub fn dmacr(self) -> Reg<Dmacr, RW>

DMA control

pub fn dmatdlr(self) -> Reg<Dmatdlr, RW>

DMA TX data level

pub fn dmardlr(self) -> Reg<Dmardlr, RW>

DMA RX data level

pub fn idr(self) -> Reg<u32, RW>

Identification register

pub fn ssi_version_id(self) -> Reg<u32, RW>

Version ID

pub fn dr0(self) -> Reg<u32, RW>

Data Register 0 (of 36)

pub fn rx_sample_dly(self) -> Reg<RxSampleDly, RW>

RX sample delay

pub fn spi_ctrlr0(self) -> Reg<SpiCtrlr0, RW>

SPI control

pub fn txd_drive_edge(self) -> Reg<TxdDriveEdge, RW>

TX drive edge

Trait Implementations

impl Clone for XipSsi

fn clone(&self) -> XipSsi

Returns a copy of the value.

pub fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for XipSsi

impl Send for XipSsi

impl Sync for XipSsi