Struct rp2040_pac2::syscfg::Syscfg

pub struct Syscfg(pub *mut u8);

Register block for various chip control signals

Implementations

impl Syscfg

pub fn proc0_nmi_mask(self) -> Reg<u32, RW>

Processor core 0 NMI source mask Set a bit high to enable NMI from that IRQ

pub fn proc1_nmi_mask(self) -> Reg<u32, RW>

Processor core 1 NMI source mask Set a bit high to enable NMI from that IRQ

pub fn proc_config(self) -> Reg<ProcConfig, RW>

Configuration for processors

pub fn proc_in_sync_bypass(self) -> Reg<ProcInSyncBypass, RW>

For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you’re feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 0…29.

pub fn proc_in_sync_bypass_hi(self) -> Reg<ProcInSyncBypassHi, RW>

For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you’re feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 30…35 (the QSPI IOs).

pub fn dbgforce(self) -> Reg<Dbgforce, RW>

Directly control the SWD debug port of either processor

pub fn mempowerdown(self) -> Reg<Mempowerdown, RW>

Control power downs to memories. Set high to power down memories. Use with extreme caution

Trait Implementations

impl Clone for Syscfg

fn clone(&self) -> Syscfg

Returns a copy of the value.

pub fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for Syscfg

impl Send for Syscfg

impl Sync for Syscfg