Struct rp2040_pac2::sio::Fifo[][src]

pub struct Fifo(pub *mut u8);

Implementations

impl Fifo[src]

pub fn st(self) -> Reg<FifoSt, RW>[src]

Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.

pub fn wr(self) -> Reg<u32, W>[src]

Write access to this core’s TX FIFO

pub fn rd(self) -> Reg<u32, R>[src]

Read access to this core’s RX FIFO

Trait Implementations

impl Clone for Fifo[src]

impl Copy for Fifo[src]

impl Send for Fifo[src]

impl Sync for Fifo[src]

Auto Trait Implementations

impl Unpin for Fifo

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized
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impl<T> Borrow<T> for T where
    T: ?Sized
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impl<T> BorrowMut<T> for T where
    T: ?Sized
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impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
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impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
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type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.