Module rp2040_pac2::pwm::regs

Structs

Ch0Cc	Counter compare values
Ch0Csr	Control and status register
Ch0Ctr	Direct access to the PWM counter
Ch0Div	INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.
Ch0Top	Counter wrap value
Ch1Cc	Counter compare values
Ch1Csr	Control and status register
Ch1Ctr	Direct access to the PWM counter
Ch1Div	INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.
Ch1Top	Counter wrap value
Ch2Cc	Counter compare values
Ch2Csr	Control and status register
Ch2Ctr	Direct access to the PWM counter
Ch2Div	INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.
Ch2Top	Counter wrap value
Ch3Cc	Counter compare values
Ch3Csr	Control and status register
Ch3Ctr	Direct access to the PWM counter
Ch3Div	INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.
Ch3Top	Counter wrap value
Ch4Cc	Counter compare values
Ch4Csr	Control and status register
Ch4Ctr	Direct access to the PWM counter
Ch4Div	INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.
Ch4Top	Counter wrap value
Ch5Cc	Counter compare values
Ch5Csr	Control and status register
Ch5Ctr	Direct access to the PWM counter
Ch5Div	INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.
Ch5Top	Counter wrap value
Ch6Cc	Counter compare values
Ch6Csr	Control and status register
Ch6Ctr	Direct access to the PWM counter
Ch6Div	INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.
Ch6Top	Counter wrap value
Ch7Cc	Counter compare values
Ch7Csr	Control and status register
Ch7Ctr	Direct access to the PWM counter
Ch7Div	INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.
Ch7Top	Counter wrap value
En	This register aliases the CSR_EN bits for all channels. Writing to this register allows multiple channels to be enabled or disabled simultaneously, so they can run in perfect sync. For each channel, there is only one physical EN register bit, which can be accessed through here or CHx_CSR.
Inte	Interrupt Enable
Intf	Interrupt Force
Intr	Raw Interrupts
Ints	Interrupt status after masking & forcing