Struct rp2040_pac2::adc::regs::Div [−][src]
Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256
Implementations
impl Div
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pub const fn int(&self) -> u16
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Integer part of clock divisor.
pub fn set_int(&mut self, val: u16)
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Integer part of clock divisor.
pub const fn frac(&self) -> u8
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Fractional part of clock divisor. First-order delta-sigma.
pub fn set_frac(&mut self, val: u8)
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Fractional part of clock divisor. First-order delta-sigma.
Trait Implementations
Auto Trait Implementations
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impl<T> Any for T where
T: 'static + ?Sized,
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T: 'static + ?Sized,
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T: ?Sized,
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T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
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T: ?Sized,
impl<T> From<T> for T
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impl<T, U> Into<U> for T where
U: From<T>,
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U: From<T>,
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U: Into<T>,
impl<T, U> TryInto<U> for T where
U: TryFrom<T>,
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U: TryFrom<T>,