1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
use crate::generic::*; #[doc = "Control and data interface to SAR ADC"] #[derive(Copy, Clone)] pub struct Adc(pub *mut u8); unsafe impl Send for Adc {} unsafe impl Sync for Adc {} impl Adc { #[doc = "ADC Control and Status"] pub fn cs(self) -> Reg<regs::Cs, RW> { unsafe { Reg::from_ptr(self.0.add(0usize)) } } #[doc = "Result of most recent ADC conversion"] pub fn result(self) -> Reg<regs::Result, RW> { unsafe { Reg::from_ptr(self.0.add(4usize)) } } #[doc = "FIFO control and status"] pub fn fcs(self) -> Reg<regs::Fcs, RW> { unsafe { Reg::from_ptr(self.0.add(8usize)) } } #[doc = "Conversion result FIFO"] pub fn fifo(self) -> Reg<regs::Fifo, RW> { unsafe { Reg::from_ptr(self.0.add(12usize)) } } #[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256"] pub fn div(self) -> Reg<regs::Div, RW> { unsafe { Reg::from_ptr(self.0.add(16usize)) } } #[doc = "Raw Interrupts"] pub fn intr(self) -> Reg<regs::Int, RW> { unsafe { Reg::from_ptr(self.0.add(20usize)) } } #[doc = "Interrupt Enable"] pub fn inte(self) -> Reg<regs::Int, RW> { unsafe { Reg::from_ptr(self.0.add(24usize)) } } #[doc = "Interrupt Force"] pub fn intf(self) -> Reg<regs::Int, RW> { unsafe { Reg::from_ptr(self.0.add(28usize)) } } #[doc = "Interrupt status after masking & forcing"] pub fn ints(self) -> Reg<regs::Int, RW> { unsafe { Reg::from_ptr(self.0.add(32usize)) } } } pub mod regs;