Struct cortex_m::peripheral::CPUID[−][src]

pub struct CPUID { /* fields omitted */ }

CPUID

Implementations

impl CPUID[src]

pub fn select_cache(&mut self, level: u8, ind: CsselrCacheType)[src]

Selects the current CCSIDR

  • level: the required cache level minus 1, e.g. 0 for L1, 1 for L2
  • ind: select instruction cache or data/unified cache

level is masked to be between 0 and 7.

pub fn cache_num_sets_ways(
    &mut self,
    level: u8,
    ind: CsselrCacheType
) -> (u16, u16)[src]

Returns the number of sets and ways in the selected cache

pub fn cache_dminline() -> u32[src]

Returns log2 of the number of words in the smallest cache line of all the data cache and unified caches that are controlled by the processor.

This is the DminLine field of the CTR register.

pub fn cache_iminline() -> u32[src]

Returns log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor.

This is the IminLine field of the CTR register.

impl CPUID[src]

pub const PTR: *const RegisterBlock[src]

Pointer to the register block

pub const fn ptr() -> *const RegisterBlock[src]

Returns a pointer to the register block (to be deprecated in 0.7)

Trait Implementations

impl Deref for CPUID[src]

type Target = RegisterBlock

The resulting type after dereferencing.

impl Send for CPUID[src]

Auto Trait Implementations

impl !Sync for CPUID

impl Unpin for CPUID

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized, [src]

impl<T> Borrow<T> for T where
    T: ?Sized, [src]

impl<T> BorrowMut<T> for T where
    T: ?Sized, [src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, [src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, [src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.